c0b0f8cb73
This reduces the size of the binary by about 6KB! This also removes filepath that were embedded into the binary (.bin) file.
377 lines
14 KiB
C
377 lines
14 KiB
C
/*
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* FreeRTOS Kernel V10.0.0
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* Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy of
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* this software and associated documentation files (the "Software"), to deal in
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* the Software without restriction, including without limitation the rights to
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* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
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* the Software, and to permit persons to whom the Software is furnished to do so,
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* subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in all
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* copies or substantial portions of the Software. If you wish to use our Amazon
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* FreeRTOS name, please do so in a fair use way that does not cause confusion.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
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* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
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* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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* http://www.FreeRTOS.org
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* http://aws.amazon.com/freertos
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*
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* 1 tab == 4 spaces!
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*/
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/*-----------------------------------------------------------
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* Implementation of functions defined in portable.h for the ARM CM4F port.
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*----------------------------------------------------------*/
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/* Scheduler includes. */
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#include "FreeRTOS.h"
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#include "task.h"
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#ifdef SOFTDEVICE_PRESENT
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#include "nrf_soc.h"
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#include "app_util.h"
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#include "app_util_platform.h"
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#endif
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#if !(__FPU_USED) && !(__LINT__)
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#error This port can only be used when the project options are configured to enable hardware floating point support.
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#endif
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#if configMAX_SYSCALL_INTERRUPT_PRIORITY == 0
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#error configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0. See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html
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#endif
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/* Constants used to detect a Cortex-M7 r0p1 core, which should use the ARM_CM7
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r0p1 port. */
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#define portCORTEX_M4_r0p1_ID ( 0x410FC241UL )
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/* Constants required to check the validity of an interrupt priority. */
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#define portFIRST_USER_INTERRUPT_NUMBER ( 16 )
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#define portMAX_8_BIT_VALUE ( ( uint8_t ) 0xff )
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#define portTOP_BIT_OF_BYTE ( ( uint8_t ) 0x80 )
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/* Constants required to set up the initial stack. */
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#define portINITIAL_XPSR (((xPSR_Type){.b.T = 1}).w)
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#define portINITIAL_EXEC_RETURN ( 0xfffffffd )
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/* Let the user override the pre-loading of the initial LR with the address of
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prvTaskExitError() in case is messes up unwinding of the stack in the
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debugger. */
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#ifdef configTASK_RETURN_ADDRESS
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#define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS
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#else
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#define portTASK_RETURN_ADDRESS prvTaskExitError
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#endif
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/* Each task maintains its own interrupt status in the critical nesting
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variable. */
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static UBaseType_t uxCriticalNesting = 0;
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/*
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* Setup the timer to generate the tick interrupts. The implementation in this
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* file is weak to allow application writers to change the timer used to
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* generate the tick interrupt.
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*/
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extern void vPortSetupTimerInterrupt( void );
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/*
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* Exception handlers.
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*/
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void xPortSysTickHandler( void );
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/*
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* Start first task is a separate function so it can be tested in isolation.
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*/
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extern void vPortStartFirstTask( void );
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/*
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* Function to enable the VFP.
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*/
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static void vPortEnableVFP( void );
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/*
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* Used to catch tasks that attempt to return from their implementing function.
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*/
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static void prvTaskExitError( void );
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/*-----------------------------------------------------------*/
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/*
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* Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure
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* FreeRTOS API functions are not called from interrupts that have been assigned
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* a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
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*/
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#if ( configASSERT_DEFINED == 1 )
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static uint8_t ucMaxSysCallPriority = 0;
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static uint32_t ulMaxPRIGROUPValue = 0;
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#endif /* configASSERT_DEFINED */
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/*-----------------------------------------------------------*/
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/*
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* See header file for description.
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*/
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StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
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{
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/* Simulate the stack frame as it would be created by a context switch
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interrupt. */
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/* Offset added to account for the way the MCU uses the stack on entry/exit
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of interrupts, and to ensure alignment. */
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pxTopOfStack--;
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*pxTopOfStack = portINITIAL_XPSR; /* xPSR */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) pxCode; /* PC */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */
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/* Save code space by skipping register initialisation. */
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pxTopOfStack -= 5; /* R12, R3, R2 and R1. */
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*pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
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/* A save method is being used that requires each task to maintain its
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own exec return value. */
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pxTopOfStack--;
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*pxTopOfStack = portINITIAL_EXEC_RETURN;
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pxTopOfStack -= 8; /* R11, R10, R9, R8, R7, R6, R5 and R4. */
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return pxTopOfStack;
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}
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/*-----------------------------------------------------------*/
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static void prvTaskExitError( void )
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{
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/* A function that implements a task must not exit or attempt to return to
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its caller as there is nothing to return to. If a task wants to exit it
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should instead call vTaskDelete( NULL ).
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Artificially force an assert() to be triggered if configASSERT() is
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defined, then stop here so application writers can catch the error. */
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configASSERT( uxCriticalNesting == ~0UL );
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portDISABLE_INTERRUPTS();
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for ( ;; );
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}
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/*-----------------------------------------------------------*/
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/*
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* See header file for description.
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*/
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BaseType_t xPortStartScheduler( void )
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{
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/* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.
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See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
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configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY );
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/* This port is designed for nRF52, this is Cortex-M4 r0p1. */
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configASSERT( SCB->CPUID == portCORTEX_M4_r0p1_ID );
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#if ( configASSERT_DEFINED == 1 )
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{
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volatile uint32_t ulOriginalPriority;
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volatile uint8_t * const pucFirstUserPriorityRegister = &NVIC->IP[0];
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volatile uint8_t ucMaxPriorityValue;
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/* Determine the maximum priority from which ISR safe FreeRTOS API
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functions can be called. ISR safe functions are those that end in
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"FromISR". FreeRTOS maintains separate thread and ISR API functions to
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ensure interrupt entry is as fast and simple as possible.
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Save the interrupt priority value that is about to be clobbered. */
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ulOriginalPriority = *pucFirstUserPriorityRegister;
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/* Determine the number of priority bits available. First write to all
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possible bits. */
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*pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
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/* Read the value back to see how many bits stuck. */
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ucMaxPriorityValue = *pucFirstUserPriorityRegister;
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/* Use the same mask on the maximum system call priority. */
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ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
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/* Calculate the maximum acceptable priority group value for the number
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of bits read back. */
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ulMaxPRIGROUPValue = SCB_AIRCR_PRIGROUP_Msk >> SCB_AIRCR_PRIGROUP_Pos;
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while ( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
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{
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ulMaxPRIGROUPValue--;
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ucMaxPriorityValue <<= ( uint8_t ) 0x01;
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}
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/* Remove any bits that are more than actually existing. */
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ulMaxPRIGROUPValue &= SCB_AIRCR_PRIGROUP_Msk >> SCB_AIRCR_PRIGROUP_Pos;
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/* Restore the clobbered interrupt priority register to its original
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value. */
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*pucFirstUserPriorityRegister = ulOriginalPriority;
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}
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#endif /* conifgASSERT_DEFINED */
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/* Make PendSV the lowest priority interrupts. */
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NVIC_SetPriority(PendSV_IRQn, configKERNEL_INTERRUPT_PRIORITY);
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/* Start the timer that generates the tick ISR. Interrupts are disabled
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here already. */
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vPortSetupTimerInterrupt();
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/* Initialise the critical nesting count ready for the first task. */
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uxCriticalNesting = 0;
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/* Ensure the VFP is enabled - it should be anyway. */
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vPortEnableVFP();
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/* Lazy save always. */
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FPU->FPCCR |= FPU_FPCCR_ASPEN_Msk | FPU_FPCCR_LSPEN_Msk;
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/* Finally this port requires SEVONPEND to be active */
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SCB->SCR |= SCB_SCR_SEVONPEND_Msk;
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/* Start the first task. */
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vPortStartFirstTask();
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/* Should never get here as the tasks will now be executing! Call the task
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exit error function to prevent compiler warnings about a static function
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not being called in the case that the application writer overrides this
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functionality by defining configTASK_RETURN_ADDRESS. */
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prvTaskExitError();
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/* Should not get here! */
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return 0;
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}
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/*-----------------------------------------------------------*/
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void vPortEndScheduler( void )
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{
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/* Not implemented in ports where there is nothing to return to.
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Artificially force an assert. */
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configASSERT( uxCriticalNesting == 1000UL );
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}
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/*-----------------------------------------------------------*/
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void vPortEnterCritical( void )
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{
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portDISABLE_INTERRUPTS();
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uxCriticalNesting++;
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/* This is not the interrupt safe version of the enter critical function so
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assert() if it is being called from an interrupt context. Only API
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functions that end in "FromISR" can be used in an interrupt. Only assert if
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the critical nesting count is 1 to protect against recursive calls if the
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assert function also uses a critical section. */
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if ( uxCriticalNesting == 1 )
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{
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configASSERT( ( SCB->ICSR & SCB_ICSR_VECTACTIVE_Msk ) == 0 );
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}
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}
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/*-----------------------------------------------------------*/
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void vPortExitCritical( void )
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{
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configASSERT( uxCriticalNesting );
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uxCriticalNesting--;
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if ( uxCriticalNesting == 0 )
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{
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portENABLE_INTERRUPTS();
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}
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}
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/*-----------------------------------------------------------*/
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/* This is a naked function. */
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static void vPortEnableVFP( void )
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{
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SCB->CPACR |= 0xf << 20;
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}
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/*-----------------------------------------------------------*/
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uint32_t ulSetInterruptMaskFromISR( void )
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{
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__asm volatile (
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" mrs r0, PRIMASK \n"
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" cpsid i \n"
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" bx lr "
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::: "memory"
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);
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}
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void vClearInterruptMaskFromISR( __attribute__( ( unused ) ) uint32_t ulMask )
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{
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__asm volatile (
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" msr PRIMASK, r0 \n"
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" bx lr "
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::: "memory"
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);
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}
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#if ( configASSERT_DEFINED == 1 )
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void vPortValidateInterruptPriority( void )
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{
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uint32_t ulCurrentInterrupt;
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uint8_t ucCurrentPriority;
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IPSR_Type ipsr;
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/* Obtain the number of the currently executing interrupt. */
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ipsr.w = __get_IPSR();
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ulCurrentInterrupt = ipsr.b.ISR;
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/* Is the interrupt number a user defined interrupt? */
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if ( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )
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{
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/* Look up the interrupt's priority. */
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ucCurrentPriority = NVIC->IP[ ulCurrentInterrupt - portFIRST_USER_INTERRUPT_NUMBER ];
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/* The following assertion will fail if a service routine (ISR) for
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an interrupt that has been assigned a priority above
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configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
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function. ISR safe FreeRTOS API functions must *only* be called
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from interrupts that have been assigned a priority at or below
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configMAX_SYSCALL_INTERRUPT_PRIORITY.
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Numerically low interrupt priority numbers represent logically high
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interrupt priorities, therefore the priority of the interrupt must
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be set to a value equal to or numerically *higher* than
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configMAX_SYSCALL_INTERRUPT_PRIORITY.
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Interrupts that use the FreeRTOS API must not be left at their
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default priority of zero as that is the highest possible priority,
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which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,
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and therefore also guaranteed to be invalid.
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FreeRTOS maintains separate thread and ISR API functions to ensure
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interrupt entry is as fast and simple as possible.
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The following links provide detailed information:
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http://www.freertos.org/RTOS-Cortex-M3-M4.html
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http://www.freertos.org/FAQHelp.html */
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configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
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}
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/* Priority grouping: The interrupt controller (NVIC) allows the bits
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that define each interrupt's priority to be split between bits that
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define the interrupt's pre-emption priority bits and bits that define
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the interrupt's sub-priority. For simplicity all bits must be defined
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to be pre-emption priority bits. The following assertion will fail if
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this is not the case (if some bits represent a sub-priority).
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If the application only uses CMSIS libraries for interrupt
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configuration then the correct setting can be achieved on all Cortex-M
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devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the
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scheduler. Note however that some vendor specific peripheral libraries
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assume a non-zero priority group setting, in which cases using a value
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of zero will result in unpredicable behaviour. */
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configASSERT( NVIC_GetPriorityGrouping() <= ulMaxPRIGROUPValue );
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}
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#endif /* configASSERT_DEFINED */
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